| 关于短沟道双栅无结型晶体管的仿真研究 |
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| 引用本文： | 吴美乐,靳晓诗,揣荣岩,刘溪,Jong-Ho Lee. 关于短沟道双栅无结型晶体管的仿真研究[J]. 半导体学报, 2013, 34(3): 034004-8 |
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| 作者姓名： | 吴美乐 靳晓诗 揣荣岩 刘溪 Jong-Ho Lee |
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| 作者单位： | School of Information Science and Engineering,Shenyang University of Technology;School of EECS Eng and ISRC(Inter-University Semiconductor Research Center),Seoul National University Shinlim-Dong Kwanak-Gu,Seoul 151-742,Korea |
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| 基金项目： | 辽宁省教育厅科学研究一般项目 |
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| 摘 要： | We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.
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| 关 键 词： | short channel effect double-gate junctionless field-effect transistor device simulation |
| 收稿时间： | 2012-07-25 |
| 修稿时间： | 2012-09-12 |
Simulation study on short channel double-gate junctionless field-effect transistors |
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| Wu Meile,Jin Xiaoshi,Chuai Rongyan,Liu Xi and Jong-Ho Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. Chinese Journal of Semiconductors, 2013, 34(3): 034004-8 |
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| Authors: | Wu Meile Jin Xiaoshi Chuai Rongyan Liu Xi Jong-Ho Lee |
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| Affiliation: | School of Information Science and Engineering, Shenyang University of Technology, Shenyang 110870, China;School of Information Science and Engineering, Shenyang University of Technology, Shenyang 110870, China;School of Information Science and Engineering, Shenyang University of Technology, Shenyang 110870, China;School of Information Science and Engineering, Shenyang University of Technology, Shenyang 110870, China;School of EECS Eng and ISRC (Inter-University Semiconductor Research Center), Seoul National University, Shinlim-Dong, Kwanak-Gu, Seoul 151-742, Korea |
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| Abstract: | We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output I-V characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed. |
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| Keywords: | short channel effect double-gate junctionless field-effect transistor device simulation |
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