| 基于FPGA和DVI视频接收器设计 |
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| 引用本文： | 张君昌,张毛毛,于乐,于洪伟. 基于FPGA和DVI视频接收器设计[J]. 微型机与应用, 2013, 32(16): 30-32 |
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| 作者姓名： | 张君昌 张毛毛 于乐 于洪伟 |
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| 作者单位： | 1. 西北工业大学电子信息学院,陕西西安,710129
2. 中国航空无线电电子研究所,上海,200233 |
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| 摘 要： | 给出了一个符合DVI1.0规范的基于FPGA的视频接收器的实现方法,该方法利用FPGA内置的PLL和IODELAY模块实现时钟恢复和相位调整,可节约数字时钟管理模块（DCM）;利用FPGA内置的ISERDES和DDR实现串/并转换,并用逻辑来实现字对齐,利用FIFO来实现通道对齐;最后经过解码,输出视频信号.与采用专用视频接口接收芯片相比,其充分利用FPGA自身的资源,提高了系统集成度,减少了资源消耗.
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| 关 键 词： | 数字视频接口 FPGA 延时单元 |
Video receiver design based on FPGA and DVI |
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| Zhang Junchang , Zhang Maomao , Yu Le , Yu Hongwei. Video receiver design based on FPGA and DVI[J]. Microcomputer & its Applications, 2013, 32(16): 30-32 |
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| Authors: | Zhang Junchang Zhang Maomao Yu Le Yu Hongwei |
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| Affiliation: | 1. Department of Electronics and Information, Northwestern Polytechnical University, Xi＇an 710129, China; 2. China National Aeronautical Radio Electronics Research Institute, Shanghai 200233, China) |
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| Abstract: | This paper presents a video receiver based on FPGA which ＂meets the DVI1.0 specification. It uses FPGA built in PLL and IODELAY module to achieve clock recovery and phase adjustment, saving valuable DCM resources. The serial data is transferred to parallel by DDR and ISERDES in FPGA. It uses logic to complete the word alignment and uses FIFO to accomplish the channel alignment. Finally, the video data is produced through decoding. Compared with a dedicated video interface receiver chip, it makes full use of FPGA own resources to improve system integration and reduce resource consumption. |
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| Keywords: | DVI FPGA IODELAY module |
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