| JESD204B接口协议中的8B/10B解码器设计 |
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| 引用本文： | 陈登,姚亚峰,欧阳靖,霍兴华. JESD204B接口协议中的8B/10B解码器设计[J]. 电视技术, 2014, 38(19) |
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| 作者姓名： | 陈登 姚亚峰 欧阳靖 霍兴华 |
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| 作者单位： | 中国地质大学(武汉)机械与电子信息学院,湖北武汉,430074 |
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| 摘 要： | JESD204B是一种用于数据转换器和逻辑器件内部高速互连的行业新标准,可支持高达12.5 Gbit/s的多通道同步和串行数据传输。设计和实现了一种符合JESD204B协议规范的8B/10B解码器,除了能够正确解码外,还包括控制字符、判断电路、数据极性检测和错误码字检测电路。利用极性信息简化了解码电路,利用组合逻辑提高了检错和极性检测速度,采取并行处理的拓扑结构加快了电路运行速度。跟其他典型电路相比,在芯片面积上缩小了近50%,最高工作频率提高了25%,满足JESD204B协议的指标要求。
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| 关 键 词： | B/B解码器 Ser Des JESDB 电路设计 |
| 收稿时间： | 2014-03-24 |
| 修稿时间： | 2014-05-06 |
Implementation of 8B/10B Decoder Based On JESD204B Interface Protocol |
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| Chen Deng,Yao Ya-feng,Ouyang Jing and Huo Xing-hua. Implementation of 8B/10B Decoder Based On JESD204B Interface Protocol[J]. Ideo Engineering, 2014, 38(19) |
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| Authors: | Chen Deng Yao Ya-feng Ouyang Jing Huo Xing-hua |
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| Affiliation: | China University of Geosciences,China University of Geosciences,China University of Geosciences,China University of Geosciences |
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| Abstract: | JESD204B is a new industry protocol used in the high speed inner link between data converter and logic component. It supports mutil-channel synchronization and serialized data transmission up to 12.5Gbps. Design and implement an 8B/10B decoder meets the JESD204B protocol. In addition to the correct decoding, the 8B/10B decoder also combines with control bit detection, running disparity detection and error detection. Running disparity information is used to reduce the decoder table. Logical circuit improved the error detecting and running disparity detecting. Parallel structure has been used to accelerate the overall speed. Comparing to the typical designs, the chip area of new design has decreased by 50% and the operating frequency has improved 26%. Completely satisfying the requirement of the JESD204B protocol. |
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| Keywords: | 8B/10B Decoder SerDes JESD204B Circuit Design |
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