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Efficient algorithm for logic design using multiplexers
Authors:Shankar   V.S.
Affiliation:Defence Electron. Res. Lab., Hyderabad;
Abstract:An algorithmic procedure has been developed for the realisation of any Boolean function F(n) of n variables with a single multiplexer of minimum size. This procedure gives the choice of control variables to be used for the realisation of the function. The algorithm is iterative in nature and very suitable for machine implementation
Keywords:
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