Ultra low power 2.4-GHz 0.35-/spl mu/m CMOS dual-modulus prescaler design |
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| Authors: | Chong-Chon Ng Kwok-Keung M Cheng |
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| Affiliation: | Dept. of Electron. Eng., Chinese Univ. of Hong Kong, China; |
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| Abstract: | This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-/spl mu/m standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW. |
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