一种200V/100A VDMOS器件开发

分析了功率MOSFET最大额定电流与导通电阻的关系,讨论了平面型中压大电流VDMOS器件设计中导通电阻、面积和开关损耗的折衷考虑,提出了圆弧形沟道布局以增大沟道宽度,以及栅氧下部分非沟道区域采用局域氧化技术以减小栅电容的方法,并据此设计了一种元胞结构。详细论述了器件制造过程中的关键工艺环节,包括栅氧化、光刻套准、多晶硅刻蚀、P阱推进等。流水所得VDMOS实测结果表明,该器件反向击穿特性良好,栅氧耐压达到本征击穿,阈值电压2.8V,导通电阻仅25mΩ,器件综合性能良好。

The Development of a 200V/100A VDMOS Device

The relation of maximum rating current and on-state resistance of power MOSFET is analyzed,and the tradeoffs between on-state resistance,area and switching loss for the design of planar medium voltage and large current VDMOS are discussed.The circular arc-shaped channel layout for a large channel width and the LOCOS under the gate oxide aimed to reduce of gate capacitance are provided,based on which a cell structure is designed.The key processes,including gate oxide fabrication,photolithography alignment,polysilicon etching and P well driving in,are discussed in detail.The measured reverse breakdown characteristic is excellent and the gate oxide withstand voltage reaches the intrinsic breakdown voltage domain.The threshold voltage is 2.8V,while the on-state resistance is only 25 m Ω.All results show that the comprehensive performance of the developed 200V/100A VDMOS is satisfactory.