| Abstract: | As device manufacturers scale their silicon technology, and processor speeds rise above 1 GHz, it's becoming common for every processor company to tout gigahertz processors. To continually improve system-level performance, system designers have begun increasing I/O performance. Some of these changes are evolutionary; some are revolutionary. The latter necessitate a change in test methodology and in the subsequent DFT. Intel's changing its processors' front-side bus from common-clock to source-synchronous (SS) signaling and increasing their bus transfer rate from less than 100 MHz to 800 megatransfers/second (1 MT/s= 1 Mbyte/s/pin). On the chipset side, Intel has upgraded its universal serial bus from 48 Mbps to 400 Mbps and has transitioned to the serial advanced technology attachment (SATA) standard at a 1.25-Gbps data rate. we show how we've solved the testing problem of the SS interface and how this self-test scheme is extendable to other high-speed I/O circuits, including high-speed serial (HSS) signaling. |
