Compact yet efficient hardware implementation of artificial neural networks with customized topology |
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| Authors: | Nadia Nedjah Rodrigo Martins da Silva Luiza de Macedo Mourelle |
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| Affiliation: | 1. Department of Electronics Engineering and Telecommunication, Faculty of Engineering, State University of Rio de Janeiro, Brazil;2. Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Brazil;1. Department of Banking and Finance, Chinese Culture University (SCE), 55, Hwa-Kang Road, Yang-Ming-Shan, Taipei 11114, Taiwan;2. Graduate Institute of Urban Planning, College of Public Affairs, National Taipei University, 151, University Rd., San Shia District, New Taipei City 23741, Taiwan;1. School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, Hubei, China;2. The National Key Laboratory for Vessel Integrated Power System Technology Dept., Naval University of Engineering, Wuhan, Hubei, China;1. Institute of Microelectronics and Information Technology, Wuhan University, Wuhan, China;2. ECE Department, University of Kentucky, USA;1. Department of Computer Science and Technology, Technological Educational Institution of Western Macedonia at Kastoria, Kastoria, Greece;2. Department of International Trade, Technological Educational Institute of Western Macedonia at Kastoria, P.O. Box 30, GR-521 00, Kastoria, Greece;3. Escuela Politécnica Superior de Zamora, Universidad de Salamanca, Salamanca, Spain;4. Department of Mathematics, College of Sciences, King Saud University, P. O. Box 2455, Riyadh 11451, Saudi Arabia;5. Laboratory of Computational Sciences, Department of Informatics and Telecommunications, Faculty of Economy, Management and Informatics, University of Peloponnese, GR-221 00 Tripolis, Greece |
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| Abstract: | There are several neural network implementations using either software, hardware-based or a hardware/software co-design. This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP). In this paper, we explore the parallelism of neural networks and allow on-the-fly changes of the number of inputs, number of layers and number of neurons per layer of the net. This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware. In order to reduce the processing time that is spent in arithmetic computation, a real number is represented using a fraction of integers. In this way, the arithmetic is limited to integer operations, performed by fast combinational circuits. A simple state machine is required to control sums and products of fractions. Sigmoid is used as the activation function in the proposed implementation. It is approximated by polynomials, whose underlying computation requires only sums and products. A theorem is introduced and proven so as to cover the arithmetic strategy of the computation of the activation function. Thus, the arithmetic circuitry used to implement the neuron weighted sum is reused for computing the sigmoid. This resource sharing decreased drastically the total area of the system. After modeling and simulation for functionality validation, the proposed architecture synthesized using reconfigurable hardware. The results are promising. |
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