FEADS: A Framework for Exploring the Application Design Space on Network Processors |
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Authors: | Rajani Pai R Govindarajan |
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Affiliation: | (1) Department of Computer Science and Automation, Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore, 560 012, India |
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Abstract: | Network processors are designed to handle the inherently parallel nature of network processing applications. However, partitioning
and scheduling of application tasks and data allocation to reduce memory contention remain as major challenges in realizing
the full performance potential of a given network processor. The large variety of processor architectures in use and the increasing
complexity of network applications further aggravate the problem. This work proposes a novel framework, called FEADS, for
automating the task of application partitioning and scheduling for network processors. FEADS uses the simulated annealing
approach to perform design space exploration of application mapping onto processor resources. Further, it uses cyclic and
r-periodic scheduling to achieve higher throughput schedules. To evaluate dynamic performance metrics such as throughput and
resource utilization under realistic workloads, FEADS automatically generates a Petri net (PN) which models the application,
architectural resources, mapping and the constructed schedule and their interaction. The throughput obtained by schedules
constructed by FEADS is comparable to that obtained by manual scheduling for linear task flow graphs; for more complicated
task graphs, FEADS’ schedules have a throughput which is upto 2.5 times higher compared to the manual schedules. Further,
static scheduling of tasks results in an increase in throughput by upto 30% compared to an implementation of the same mapping
without task scheduling. |
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Keywords: | Cyclic scheduling design space exploration network processor programming model performance Evaluation petri Nets |
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