| A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS |
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| 作者姓名： | 张章 袁宇丹 郭亚炜 程旭 曾晓洋 |
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| 作者单位： | State Key Laboratory of ASIC & System;Fudan University; |
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| 基金项目： | supported by the National High Technology Research and Development Program of China(No.2009AA011600); the Project for Young Scientists Fund of Fudan University,China(No.09FQ33); the State Key Laboratory ASIC & System(Fudan University), China(No.09MS008) |
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| 摘 要： | A 10-bit 30-MS/s pipelined analog-to-digital converter(ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic device...
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| 关 键 词： | 兰艺 |
| 收稿时间： | 2015-08-18 |
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