DA算法结构改进及其实现

在FPGA的DSP处理中，传统上基于FPGA查找表(LUT)算法在关键通道上存在一个或多个进位传播链，对速度性能形成较大影响。就如何减小或取消FPGA上基于LUT的DA算法关键通道上进位传播作探讨，并提出新的算法，这种方法大大加速了基于DA算法的DSP处理，有较高的性价比。

DA Architecture Improvement and Implement

About implementing digital signal processing (DSP) functions in FPGAs, traditional DA architectures based on lookup table(LUT) contain one or more carry propagation chains in the critical path that dictates the fastest time at which an entire design can run. We describe a novel technique that can reduce or eliminate the carry propagate chain from the critical path in LUT based DA architectures on FPGAs, and put forward a new technique that has great potential in speeding up DSP applications based on DA. The analysis shows that the designs have a lower cost performance ratio (indicating better performance) than traditional DA designs. We also show that the 8-bit (r = 8) designs offer a good compromise between cost and performance.