| AES密码算法的FPGA优化设计 |
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| 引用本文： | 武玉华,徐玲杰,周玉坤,李莉. AES密码算法的FPGA优化设计[J]. 通信技术, 2008, 41(10) |
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| 作者姓名： | 武玉华 徐玲杰 周玉坤 李莉 |
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| 作者单位： | 北京电子科技学院,北京,100070 |
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| 摘 要： | 主要介绍基于FPGA的AES算法优化设计.从AES加密算-法的介绍、Rijndael算法的描述、AES密码算法的优化设计、AES密码算法的FPGA实现、PC机与FPGA的通信设计等方面论述实现硬件加密的方法,手段、可行性和优越性;实现了基于FPGA技术的Rijndacl算法,并给出了相应的各种仿真波形和结果.
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| 关 键 词： | 高级加密标准 现场可编程逻辑门阵列 优化 通用异步接收器/发送器 |
Optimized Design of AES Encryption Based on FPGA |
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| WU Yu-hua,XU Ling-jie,ZHOU Yu-kun,LI Li. Optimized Design of AES Encryption Based on FPGA[J]. Communications Technology, 2008, 41(10) |
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| Authors: | WU Yu-hua XU Ling-jie ZHOU Yu-kun LI Li |
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| Affiliation: | WU Yu-hua,XU Ling-jie,ZHOU Yu-kun,LI Li (Beijing Electronic Science , Technology Institute,Beijing 100070,China) |
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| Abstract: | This paper principally presents the optimized design of FPGA-based AES algorithm, and describes the AES algorithm, the Rijndael algorithm, optimization of AES algorithm, the realization of AES cipher based on FPGA, the communication programmable logic device function of PC and FPGA, including the realization of Rijndeal algorithm based on FPGA technology. Finally it gives various corresponding simulation results and waveforms output. |
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| Keywords: | AES FPGA Optimization UART |
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