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Efficient shared-memory support for parallel graph reduction
Authors:Andrew J. Bennett  Paul H.J. Kelly
Affiliation:

Department of Computing, Imperial College of Science, Technology and Medicine, 180 Queen's Gate, London SW72BZ, UK

Abstract:This paper presents the results of a simulation study of cache coherency issues in parallel implementations of functional programming languages. Parallel graph reduction uses a heap shared between processors for all synchronisation and communication. We show that a high degree of spatial locality is often present and that the rate of synchronisation is much greater than for imperative programs. We propose a modified coherency protocol with static cache line ownership and show that this allows locality to be exploited to at least the level of a conventional protocol, but without the unnecessary serialisation and network transactions this usually causes. The new protocol avoids false sharing, and makes it possible to reduce the number of messages exchanged, but relies on increasing the size of the cache lines exchanged to do so. It is, therefore, of most benefit with a high-bandwidth interconnection network with relatively high communication latencies or message handling overheads.
Keywords:Cache organisation   Simulation   Declarative languages   Shared-memory
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