首页 | 本学科首页   官方微博 | 高级检索  
     

边界扫描技术在VLSI电路设计中的应用研究
引用本文:王燕.边界扫描技术在VLSI电路设计中的应用研究[J].计算机测量与控制,2006,14(10):1307-1309.
作者姓名:王燕
作者单位:南京电子技术研究所,江苏,南京,210013
摘    要:边界扫描技术(BST)是一种新型的VLSI电路测试方法,但在扫描链路的设计中如何将不同厂家、不同型号、不同工作电压的BS器件实现JTAG互连,如何将边界扫描测试、在线编程和仿真结合起来一直是一个亟待解决的问题;为解决上述问题,在大规模集成电路设计中采用逻辑可编程扫描链方法,利用边界扫描技术对电路板进行测试,实验证明采用逻辑可编程扫描链方法可有效的解决测试与在线编程(或在线仿真)的兼容问题。

关 键 词:边界扫描  逻辑可编程扫描链方法  验证板
文章编号:1671-4598(2006)10-1307-03
收稿时间:2006-01-24
修稿时间:2006-03-04

Research on Designing VLSI Circuits Based on Boundary-scan Technology
Wang Yan.Research on Designing VLSI Circuits Based on Boundary-scan Technology[J].Computer Measurement & Control,2006,14(10):1307-1309.
Authors:Wang Yan
Affiliation:Nanjing Research Institute of Electronics Technology, Nanjing 210013, China
Abstract:Boundary-scan technology(BST) is a new method for testing VLSI circuits.When designing the boundary scan(BS) chain,we are faced with some problems requiring solution immediately,such as how to realize the JTAG interconnection among the BS devices coming from different manufactures,of different types and having different working voltages,as well as how to combine BS test,in-system-programming and in-system-emulation together.To solve these problems,the method of logic programmable BS chain is applied in the design of VLSI circuits.Some experiments are done,which prove it's an effective way to resolve the compatibility between test and in-system-programming(or in-system-emulation).
Keywords:boundary scan  method of logic programmable BS chain  test board
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号