DC analysis of current mode logic

A closed-form solution to finding the optimum signal swing for CML (current-mode logic) is illustrated, based on a few parameters of the minimum geometry transistor in a given technology. A simplified transistor model is used to develop the concept of noise margin optimized for both transistor and circuit parameters. It is shown that the voltage swing of the CML gate is not an arbitrary choice for the circuit designer but is deterministic. The effects of gate fan-in and series gating are then included as part of the closed-form solution, yielding an optimized set of parameters for defining all logic functions. Calculation of the maximum fan-out as well as bias regulators and calculation of the voltage drops in the power buses of chip layouts are treated. The procedure described has been used to develop a CML cell library for producing high-performance interface and networking circuits