高速多通道大容量数据采集与传输系统研究

为实现高速多通道数据采集的大容量存储，对FPGA与DDRSDRAM接口技术进行了研究。从A／D转换后数据传输路径的角度出发，分析了FIFO和DDRSDRAM的时序和工作原理，在各通道同步采集的前提下实现了FPGA对DDRSDRAM的控制，给出了ARM与FPGA通信的设计方法，实现了ARM和FPGA共享双口RAM存储器的结构，最后进行了测试与验证。测试结果表明，该系统在通道数为8、采样率为20MHz／通道、存储深度为4Mwords／通道的条件下稳定工作。

Research of large capacity data acquisition and transmission system with high-speed and multi-channel

An interface technology between FPGA and DDR SDRAM is discussed in this paper,which is used to realize the mass storage of a high-speed and multi-channel data acquisition. By implementing the DDR SDRAM controller, the operating timing sequence and the theory of FIFO and DDR SDRAM is analyzed on the basis of the data transmission path of A/D converter＇s the DDR SDRAM is controlled by FPGA on the premise of synchronous acquisition of each chan- nel. A communication method between ARM and FPGA is presented to achieve the purpose of sharing the dual-port RAM structure of them. Testing and validation for the experiments were carried out. The testing results show that the system with total 8 channels,20 MHz sampling rate per channel,4 Mwords/chnanel,and it with high reliability.