| Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer |
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| 引用本文： | Xu Yong,Wang Zhigong,Qiu Yinghu,Li Zhiqun,Hu Qingsheng,and Min Rui. Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer[J]. 半导体学报, 2005, 26(9): 1711-1715 |
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| 作者姓名： | Xu Yong Wang Zhigong Qiu Yinghu Li Zhiqun Hu Qingsheng and Min Rui |
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| 作者单位： | [1]东南大学射频与光电集成电路研究所,南京210096 [2]解放军理工大学理学院,南京211101 |
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| 摘 要： | An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
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| 关 键 词： | PLL frequency synthesizer dual-modulus prescaler programmable & pulse swallow divider |
| 文章编号： | 0253-4177（2005）09-1711-05 |
| 收稿时间： | 2005-01-16 |
| 修稿时间： | 2005-05-09 |
Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer |
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| Xu Yong, Wang Zhigong, Qiu Yinghua, Li Zhiqun, Hu Qingsheng, Min Rui ( Instituteof RF-. Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer[J]. Chinese Journal of Semiconductors, 2005, 26(9): 1711-1715 |
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| Authors: | Xu Yong Wang Zhigong Qiu Yinghua Li Zhiqun Hu Qingsheng Min Rui ( Instituteof RF- |
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| Affiliation: | Xu Yong, Wang Zhigong, Qiu Yinghua, Li Zhiqun, Hu Qingsheng, Min Rui (1 Instituteof RF- |
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| Abstract: | An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility. |
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| Keywords: | PLL frequency synthesizer dual-modulus prescaler programmable pulse swallow divider |
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