| 基于线性插值法图像缩放的设计与FPGA实现 |
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| 引用本文： | 莫迪涵,杜慧敏,沈绪榜.基于线性插值法图像缩放的设计与FPGA实现[J].西安邮电学院学报,2013(3):52-55. |
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| 作者姓名： | 莫迪涵 杜慧敏 沈绪榜 |
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| 作者单位： | 西安邮电大学电子工程学院;西安微电子技术研究所 |
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| 基金项目： | 国家自然科学基金重点资助项目(90607008);陕西省工业攻关基金资助项目(2011k06-47) |
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| 摘 要： | 针对通用目的的图像缩放处理器对硬件资源要求较高的问题,提出一种占用资源较少的图像缩放硬件实现方案。根据线性插值算法进行图像缩放的硬件设计,其中行、列的插值运算共用一套运算电路,且该运算电路采用流水线结构来实现,从而在减少电路面积的同时提高缩放的速度。采用Design Compiler工具对电路进行综合,之后下载到Virtex XC6VLX550TFPGA芯片上进行验证。综合验证结果表明该方案与Catmull_Rom三次样条插值法设计相比,速度相当,但电路面积减少了4/5。
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| 关 键 词： | 图像放缩 线性插值 FPGA 流水线 |
Design and implement of image scaling based on linear interpolation |
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| MO Dihan,DU Huimin,SHEN Xubang.Design and implement of image scaling based on linear interpolation[J].Journal of Xi'an Institute of Posts and Telecommunications,2013(3):52-55. |
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| Authors: | MO Dihan DU Huimin SHEN Xubang |
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| Affiliation: | 1.School of Electronics Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China; 2.Xi’an Microelectronics Research Institute,Xi’an 710054,China) |
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| Abstract: | The general purpose of image scaling requires excessive hardware resources.A hardware implementation scheme for image scaling with lower resources consumption is proposed in this paper.Firstly,a hardware design of image scaling based on linear Interpolation algorithm is proposed.In order to reduce the resources consumption and to improve the speed of scaling,the interpolation of rows and columns calculated by a common calculating circuit is implemented by a pipeline and the design is synthesized by Synopsys' Design Compiler.Finally,the design is validated on Xilinx Virtex XC6VLX550T FPGA chip.The results show that the scheme proposed in this paper can reduce circuit area by 4/5 without sacrificing the speed compared with the design based on Catmull_Rom three spline interpolations. |
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| Keywords: | image scaling linear interpolation FPGA pipeline |
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