A 256-Mb DRAM with 100 MHz serial I/O ports for storage of movingpictures |
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| Authors: | Kotani H. Akamatsu H. Naito Y. Fujii T. Iwata T. Tsuji T. Itoh Y. Shimizu N. Hirase J. Shibata Y. Yamashita K. Hori T. Fujita T. |
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| Affiliation: | Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka; |
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| Abstract: | A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-μm CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access |
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