| 基于FPGA的DSP外部总线接口设计 |
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| 引用本文： | 高路,周起华,张琦. 基于FPGA的DSP外部总线接口设计[J]. 制导与引信, 2011, 32(2): 20-23 |
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| 作者姓名： | 高路 周起华 张琦 |
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| 作者单位： | 上海无线电设备研究所,上海,200090 |
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| 摘 要： | 文章针对FPGA与DSP之间的总线协议,建立FPGA与DSP总线通信的接口框架,根据不同类型的DSP设计相应的时序协调电路,保证DSP与外部器件之间高速稳定的数据通信。使用该设计方法在Quartus Ⅱ进行仿真,时序满足DSP的读写时序要求。实验证明该方法满足实际使用要求。
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| 关 键 词： | 数字信号处理 总线 接口 |
DSP External Bus Interface Design Based on FPGA |
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| GAO Lu,ZHOU Qi-hua,ZHANG Qi. DSP External Bus Interface Design Based on FPGA[J]. Guidance & Fuze, 2011, 32(2): 20-23 |
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| Authors: | GAO Lu ZHOU Qi-hua ZHANG Qi |
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| Affiliation: | GAO Lu,ZHOU Qi-hua,ZHANG Qi(Shanghai Radio Equipment Research Institute,Shanghai 200090,China) |
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| Abstract: | The bus interface frame is built in the FPGA,and the time-sequence harmonized circuit is designed according to different object which is accessed by the DSP,which ensure that the DSP could access outer bus interface with highest speed.Finally,simulations are done,which indicate that the time-sequence is satisfied with the DSP demand,and the time margin is enough to the requirement of application. |
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| Keywords: | digital signal processing bus interface |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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