基于FPGA的新型数字频率计的设计与仿真

基于测频原理及FPGA的设计思想，给出了一种新型数字测频系统的设计方案，系统采用VHDL语言，运用自顶向下的设计思想，采取将系统按功能逐层分割的层次化设计方法。在具体实现上，以FPGA为中央处理器对被测频率信号进行周期采样，通过调用QuartusⅡ的宏功能模块进行占空比计算，将所得占空比数值传输给128×64的液晶显示器，实现显示被测信号占空比数值和波形的设计优化目的。硬件测试仿真结果验证了数字测频系统的有效性和可行性。

Design and Simulation of New Digital Cymometer Based on FPGA

Based on the principle of frequency measurement and the programming thought of FPGA, a new digital cymometer which uses VHDL language with up to bottom design and divides layers by functions is proposed. In terms of realization, this digital cymometer takes sample of the measured frequency signal by FPGA controlling, and makes duty ratio calculation by calling for the function modules in Quartus Ⅱ, then transmits the value of duty ratio to the 128×64 LCD. It achieves in the show of the value of duty ratio and the waveform of measured frequency signal. The testing simulation results show the effectiveness and feasibility of this digital cymometer.