高可靠性TMS320C30专用信号处理硬件设计

设计高可靠性的ＤＳＰ（数字信号处理器）应用系统是ＤＳＰ芯片实际应用中所遇到的关键问题。本文论述了基于ＴＭＳ３２０Ｃ３０高速信号处理器的高可靠性ＤＳＰ应用系统的设计方法，介绍了ＴＭＳ３２０Ｃ３０信号处理模板的主从式结构，可变等待状态产生电路等关键电路设计技巧，并详细讨论了软件防“跑飞”，存贮区重叠设计和防误改写程序ＲＡＭ区的三种抗干扰措施。实验结果表明，三种抗干扰方法可有效地解决ＤＳＰ应用中所遇到的因干扰造成系统“风机”等问题。

The Hardware Design of a High Reliability Digital Signal Processor TMS320C30

To design the high reliability DSP(Digital Signal Processing) applied system is the key problem in the application of DSP chip. This paper gives a design method of the TMS320C30-based on high reliability DSP applied system. The key design techniques in hardware, such as master-slaver structure and variable wait-state generating circuit, have been introduced. Three kinds of anti-interference methods,namely, preventing program-sensitive fault, overlapped memories technique and preventing form rewriting program RAM,have been described in detail. Experiment results show that these methods can solve the problem of system halt due to the interference in the application of DSP chip.