Noise in digital dynamic CMOS circuits |
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Authors: | Larsson P Svensson C |
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Affiliation: | Dept. of Phys. & Meas. Technol., Linkoping Inst. of Technol.; |
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Abstract: | Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits |
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