Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core |
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| Authors: | Deleganes DJ Barany M Geannopoulos G Kreitzer K Morrise M Milliron D Singh AP Wijeratne S |
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| Affiliation: | Intel Corp., Hillsboro, OR, USA; |
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| Abstract: | The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design. |
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