基于ARM7TDMI的cache控制器电路

针对ARM7TDMI内核的特点,提出了一种高速缓存(cache)控制器的电路实现方案.主要应用Verilog硬件描述语言对cache控制器进行了行为级描述,通过了前端仿真和综合后的联合仿真,比较了嵌入式系统中有无cache的工作效率,并给出了实验结果.实验结果表明,系统中加入cache电路以后存储性能会有显著提高.

A Cache Controller Circuit Based on ARM7TDMI

According to design characteristic of ARM7TDMI core, we put forward an circuit implementation of cache controller. In this article we use the verilog HDL to behaviorally describe the cache controller, and pass the front end simulation and back end simulation. Performance benefits are evaluated with Dhrystone benchmarks. At last the experiment result demonstrates its correct function.