基于FPGA的高斯滤波器的快速实现

为了降低高斯滤波器的结构复杂性,提高计算速度,提出基于FPGA的串联多级均值滤波器快速逼近高斯滤波器的方法,通过VHDL语言实现滤波器设计并给出在FPGA上的仿真实现结果.该方法简化了高斯滤波器的设计结构,提高了响应速度.实验结果表明：整个滤波器的实现时间可以跟FPGA的工作频率同步,满足了数据流实时性的要求.该设计可以应用到实时的信号处理过程中.

Fast Implementation of Gaussian Filter With FPGAs

In order for lowering the structure complexity of Gaussian filter and improving the calculation speed,this paper presents a method for a series multi-stage mean filter fast approaching to Gaussian filter based on FPGAs,implements the filter design using VHDL and gives the simulation implementation.The experimental results show that the implementing time of the overall filter can be synchronous with the FPGAs’operation frequency,thus meeting the real-time requirements for data stream,which means the design can be applied to the real-time signal processing.