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An 8-bit, 200 MSPS Folding and Interpolating ADC
Authors:Øystein Moldsvor  Geir S. Østrem
Affiliation:(1) Nordic VLSI ASA, Vestre Rosten 81, N-7075 TILLER, NORWAY
Abstract:An 8-bit, 200 MSPS folding and interpolating analog-to-digitalconverter, ADC, has been implemented in a 1.2 µmBiCMOS-process. It achieves 7.5 effective bits with a power dissipationof 575mW. The active area is 4mm2. The implementationand measured results are presented. A simple analytical modelfor the interpolation-induced nonlinearity in a folding and interpolatingADC using sinusoidal folding is presented. The bowing of thereference ladder due to interaction with the input stages isanalyzed, and analytical models are derived.
Keywords:ADC  folding and interpolation  BiCMOS  high speed
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