基于BLF时钟的RFID低功耗数字基带设计

提出了一种符合ISO/IEC 18000-6C协议中关于时序规定的射频识别(RFID)无源标签芯片低功耗数字基带处理器的设计.基于采用模拟前端反向散射链路频率(BLF)时钟的方案,将BLF的二倍频设置为基带中的全局时钟,构建BLF和基带数据处理速率之间的联系;同时在设计中采用门控时钟和行波计数器代替传统计数器等低功耗策略.芯片经TSMC 0.18 μmCMOS混合信号工艺流片,实测结果表明,采用该设计的标签最远识别距离为7 m,数字基带动态功耗明显降低,且更加符合RFID协议的要求.

Design of a BLF Clock Based RFID Low-Power Digital Baseband

A design of the low-power digital baseband processor of passive radio frequency identification (RFID) tag chip which meets the requirements of ISO/IEC 18000-6C on timing was presented.Based on the strategy of backscatter link frequency (BLF) clock provided by analog front end,the double frequency of the BLF was set as the global clock in the baseband to build the relationship between the BLF and the processing rate of the baseband.Meanwhile,the clock gating and ripple counter were adopted to replace the low power consumption strategies such as the traditional counter.The chip was fabricated with the TSMC 0.18 μm CMOS mixed signal process.The experimental measurement results show that the read range of the tag using the baseband structure design is up to 7 m.This design of the digital baseband has a significant reduction in dynamic power consumption and better compatibility with the RFID protocol.