45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.

Thermal Stress Analysis for the Low-k Dielectric Layers of Cu Interconnects in a 45 nm Chip

The fragile low-k dielectric layers of Cu interconnects in an advanced chip are prone to failure damage due to the higher thermomechanical stress during the chip packaging,resulting in a problem of the chip package interaction (CPI).The 3D thermal stress analysis for a 45 nm chip was performed by the finite element method with sub-modeling technology and the interconnects were simplified as an effective thin layer in the global model.The effects of PI opening,copper pillar diameter,solder height and Ni-layer thickness on the stress in the low-k dielectric layers of Cu/low-k interconnects during the flip-chip reflow process of the chip were studied by this method.The analysis results show that the stress of the low-k dielectric in the middle layers of interconnects is in high failure risk due to the relatively higher stress,which is consistent with the reported experimental results.The effects of the four factors on the stress in low-k layers can be ranked as:solder height ＞ PI opening ＞ copper pillar diameter ＞ Nilayer thickness.