| 基于FPGA的高速AD采样设计 |
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| 引用本文： | 齐红涛,苏涛.基于FPGA的高速AD采样设计[J].航空兵器,2010(1):35-39. |
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| 作者姓名： | 齐红涛 苏涛 |
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| 作者单位： | 西安电子科技大学雷达信号处理国家重点实验室,西安,710071 |
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| 摘 要： | 随着雷达技术及现代宽带通信技术的发展,高速ADC在数字化宽带接收器的设计中起了重要作用。本文提出基于FPGA的高速AD采样设计,给出了基于FPGA的高速采样时钟设计方案以及FPGA对时钟芯片AD9516_4与ADC的配置设置,并对采样结果有效位数进行测定。结果证明该设计灵活、简单、通用性强。
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| 关 键 词： | FPGA 高速AD AD9516_4有效位数 |
Design of High AD Sampling Based on FPGA |
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| QI Hong-tao,SU tao.Design of High AD Sampling Based on FPGA[J].Aero Weaponry,2010(1):35-39. |
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| Authors: | QI Hong-tao SU tao |
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| Affiliation: | (National Key Lab of Radar Signal Processing,Xidian University,Xi＇an 710071,China) |
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| Abstract: | Along with the development of the technology of radar and modern wide band communications,high ADC played an important role in the design of digital wide band receiver.This paper gives a design of high AD sampling based on FPGA,the high sampling clock based on FPGA and the configured chips of AD9516_4 and ADC by FPGA.Effective Number Of Bits（ENOB） of the sampling result are measured.The result shows that the design is flexible,simple and general-purpose. |
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| Keywords: | FPGA |
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