高密度低寄生电感硅基半导体电容器的设计及验证

采用在半导体材料表面深刻蚀三维图形以形成稳固蜂窝结构的方法,研究了一种适用于解决高频电路和系统级封装中串扰耦合问题的高密度、低寄生电感、制作及排布容易的硅基电容。结果显示,所制作的电容,其密度可增大至普通平面半导体电容的10倍以上,并较大程度地降低了电容的寄生电感,使其性能大大优于常用商业陶瓷电容,更适用于高频电路和系统级封装中的有效退耦。

Design and validation of high density and low parasitic inductance semiconductor silicon-based capacitor

Introducing the methodology of deep etching 3D patterns to form stable honeycomb structures,a new silicon-based capacitor was investigated.This capacitor possesses the characteristics of high density,low parasitic inductance,easy to fabricate and layout,so it is suitable for solving the crosstalk and decoupling problems in high frequency circuits and system-in-packages.The test results show that the capacitance density is increased above 10 times higher than that of normal plane semiconductor capacitors,and...