Ties that bind

VHDL designers can take advantage of the advanced verification features of SystemVerilog thanks to the bind function in the newer language. One of the most important languages to emerge for advanced design and verification is SystemVerilog. This language offers a rich set of features for testbench automation, applying native assertions, functional coverage and constrained random test generation. These features make SystemVerilog increasingly appealing to VHDL users who have a number of verification-oriented features at their disposal but need to implement a more efficient functional verification methodology for complex designs