基于FPGA的数据速率及格式变换的设计与实现

为了解决数字通信中连续数据到定长帧的转换问题,设计了一个具有数据速率和结构变换功能的现场可编程门阵列(FPGA)接口变换模块,该模块包含3个核心部分:缓存单元、速率变换和帧控制逻辑,缓存单元选用了方便实用的异步FIFO来实现,速率变换部分采用了5/6小数分频方式大大节省了FPGA内部资源,帧控制逻辑单元严格定义了读FIFO的使能格式和时序,最后进行了软件的功能和时序仿真。实际应用结果表明,该模块能够准确地对数据速率和格式进行变换,实现了预期的功能。

Design and implementation of data rate and format conversion based on FPGA

In order to solve the problem of the conversion from continuous data to fixed-length frame in the digital communication, the interface conversion module based on field-programmable gate array（FPGA） with the function of data rate and structure transformation was designed,including three important parts：cache unit,rate conversion and frame control logic. The convenient asynchronous FIFO was selected to achieve the function of cache unit. The five-sixths fractional frequency was used for the rate conversion unit to save the FPGA resource. The read enable format and time sequence of FIFO were defined by the frame control logic unit strictly. The time sequence and the function of the software were simulated finally. The practical application shows that the module can finish the conversion of data rate and structure transformation accurately, and achieve the expected function.