Low-power integrating frequency difference-to-voltage converter with applications in injection-locked FLL

This paper presents a new integrating frequency difference-to-voltage converter (iFDVC) with applications in injection-locked frequency-locked loops (FLLs). The proposed iFDVC features low power consumption, high frequency sensitivity, a zero static frequency error, and a low sensitivity to PVT (process, voltage, and temperature) uncertainty. A detailed analysis of the time and frequency-domain behaviour of the iFDVC is presented. The effectiveness of the iFDVC is studied by embedding it in a FLL with a relaxation oscillator. To shorten locking process without sacrificing frequency accuracy, injection-locking is employed. The loop dynamics of the FLL with and without injection-locking are analyzed. The simulation results of an injection-locked FLL with the proposed iFDVC designed in an IBM 130 nm 1.2 V CMOS technology demonstrate that the injection-locked FLL has a lock time 4.5 times smaller and an acquisition range 59 times larger as compared with those of the corresponding FLL without injection-locking while consuming 60 \(\upmu\)W only. The iFDVC was also implemented using off-shelf components and its performance was validated using measurement results.