A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture |
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Authors: | Hirose T Kuriyama H Murakami S Yuzuriha K Mukai T Tsutsumi K Nishimura Y Kohno Y Anami K |
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Affiliation: | Mitsubishi Electr. Corp., Hyogo; |
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Abstract: | A 20 ns 4-Mb CMOS SRAM operating at a single supply voltage of 3.3 V is described. The fast access time has been achieved by a newly proposed word-decoding architecture and a high-speed sense amplifier combined with the address transition detection (ATD) technique. The RAM has the fast address mode, which achieves quicker than 10-ns access, and the 16-b parallel test mode for the reduction of test time. A 0.6-μm process technology featuring quadruple-polysilicon and double-metal wiring is adopted to integrate more than 16 million transistors in a 8.35-mm×18.0-mm die |
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