RNS-based implementation of 8 /spl times/ 8 point 2D-DCT over field-programmable devices [image compression] |
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| Authors: | Fernandez PG Lloris A |
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| Affiliation: | Departamento de Electronica y Tecnologia de Cornputadores, Campus Universitario Fuentenueva, Granada, Spain; |
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| Abstract: | A new implementation of an 8 /spl times/ 8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS) is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system. |
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