| 基于CPLD的EPP并行接口设计 |
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| 引用本文： | 李振杰,刘宁宁,米立红.基于CPLD的EPP并行接口设计[J].微计算机应用,2006,27(2):251-253. |
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| 作者姓名： | 李振杰 刘宁宁 米立红 |
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| 作者单位： | 北京军区通信训练大队,北京,100093 |
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| 摘 要： | 详细介绍了一种在CPLD控制下实现的微型机EPP并行接口设计方案。CPLD的接口时序逻辑控制功能采用状态机工作方式实现，并给出了用VHDL编写的主要源代码。通过调试，该方案已成功应用于作者所开发的传感器数据采集系统，达到了良好的工程应用效果。
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| 关 键 词： | EPP并口 |
| 收稿时间： | 2004-04-02 |
| 修稿时间： | 2004-04-02 |
The Design of EPP Parallel Interface Based on CPLD |
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| LI Zhenjie,LIU Ningning,MI Lihong.The Design of EPP Parallel Interface Based on CPLD[J].Microcomputer Applications,2006,27(2):251-253. |
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| Authors: | LI Zhenjie LIU Ningning MI Lihong |
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| Affiliation: | A Military Unit of Communication in BeiJing Military Area, BeiJing, 100093 |
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| Abstract: | This paper provides a scheme of EPP parallel interface controlled by CPLD. State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given. After testing, this scheme was used successfully in data acquisition system of serusors developed by author, and get a good result in practical application. |
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| Keywords: | CPLD VHDL |
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