| 高速并行Reed-Solomon编解码器 |
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| 引用本文： | 谭丹,聂雅琴,蒋燕妮.高速并行Reed-Solomon编解码器[J].国外电子元器件,2008,16(12). |
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| 作者姓名： | 谭丹 聂雅琴 蒋燕妮 |
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| 作者单位： | 武汉大学,电子信息学院,湖北,武汉,430079 |
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| 摘 要： | 采用多路复用流水线的思想,设计基于FPGA仿真测试的RS编解码的改进IBM算法,使用Verilog硬件编程语言实现,进一步提高RS编解码器的运行速度及纠错能力,扩大应用范围.系统设计的时序仿真表明解码器8路复用后的数据率高达116.65 b/s,最大纠错能力为7字节/204字节,达到良好效果.
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| 关 键 词： | 编码器 差错 控制/解码器 多路复用 现场可编程门阵列 |
High speed parallel Reed-Solomon codec |
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| TAN Dan,NIE Ya-qin,JIANG Yan-ni.High speed parallel Reed-Solomon codec[J].International Electronic Elements,2008,16(12). |
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| Authors: | TAN Dan NIE Ya-qin JIANG Yan-ni |
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| Affiliation: | TAN Dan,NIE Ya-qin,JIANG Yan-ni(School of Electronic Information,Wuhan University,WuHan 430079,China) |
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| Abstract: | In order to raise RS codec running speed and the ability of error correcting,expand its application,an improved IBM algorithm of RS codec based on FPGA emulational test is designed.And it adopts pipeline and multiplexing technology.The timing simulatiom of this design indicates that the processing speed of the impoved decoder can reach 116.65bps with a maximum error correcting ratio of 7/204 bytes when the multiplexing number is 8. |
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| Keywords: | encoder error control/decoder multiplexer field programmable gate array |
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