| A Fractional-N CMOS DPLL with Self-Calibration |
| |
| 作者姓名： | Liu Sujuan Yang Weiming Chen Jianxin Cai Liming Xu Dongsheng |
| |
| 作者单位： | Optoelectronics Laboratory,Beijing University of Technology,Beijing 100022,China;Optoelectronics Laboratory,Beijing University of Technology,Beijing 100022,China;Optoelectronics Laboratory,Beijing University of Technology,Beijing 100022,China;China Integrated Circuit Design Center,Beijing 100015,China;China Integrated Circuit Design Center,Beijing 100015,China |
| |
| 基金项目： | 国家高技术研究发展计划资助项目(批准号:2002AA1Z1290)~~ |
| |
| 摘 要： | A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented.The self-calibration technique is employed to acquire wide lock range,low jitter,and fast acquisition.The DPLL works from 60 to 600MHz at a supply voltage of 1.8V.It also features a fractional-N synthesizer with digital 2nd-order sigma-delta noise shaping,which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum.The DPLL has been implemented in SMIC 0.18μm 1.8V 1P6M CMOS technology.The peak-to-peak jitter is less than 0.8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
|
| 关 键 词： | digital phase-locked loop phase-frequency detector self-calibration voltage controlled oscillator fractional-N |
| 文章编号： | 0253-4177（2005）11-2085-07 |
| 收稿时间： | 2004-11-27 |
| 修稿时间： | 2005-07-25 |
A Fractionai-N CMOS DPLL with Self-Calibration |
| |
| Liu Sujuan,Yang Weiming,Chen Jianxin,Cai Liming,Xu Dongsheng.A Fractional-N CMOS DPLL with Self-Calibration[J].Chinese Journal of Semiconductors,2005,26(11):2085-2091. |
| |
| Authors: | Liu Sujuan Yang Weiming Chen Jianxin Cai Liming and Xu Dongsheng |
| |
| Affiliation: | Optoelectronics Laboratory,Beijing University of Technology,Beijing 100022,China;Optoelectronics Laboratory,Beijing University of Technology,Beijing 100022,China;Optoelectronics Laboratory,Beijing University of Technology,Beijing 100022,China;China Integrated Circuit Design Center,Beijing 100015,China;China Integrated Circuit Design Center,Beijing 100015,China |
| |
| Abstract: | |
| |
| Keywords: | digital phase-locked loop phase-frequency detector self-calibration voltage controlled oscillator fractional-N |
| 本文献已被 CNKI 维普 等数据库收录！ |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |
|
