Hot-carrier effects and reliable lifetime prediction in deepsubmicron N- and P-channel SOI MOSFETs |
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Authors: | Shing-Hwa Renn Pelloie J-L Balestra F |
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Affiliation: | Lab. de Physique des Composants & Semicond., CNRS, Grenoble; |
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Abstract: | Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 μm down to 0.1 μm. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (Vg≈Vd ), maximum substrate current (Vg≈Vd/2) and parasitic bipolar transistor (PBT) action (Vg≈0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range |
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