一种10位50MS/s两级逐次逼近流水线混合型A/D转换器

本文在0.18μm CMOS工艺下,实现了一款10位50MS/s两级逐次逼近流水线混合型模数转换器（pipeline SAR ADC）。其由基于逐次逼近的增益模数单元和逐次逼近ADC组成,并采用1位冗余位放宽了子模数转换器的比较误差。通过采用逐次逼近结构,增益减半MDAC技术,动态比较器及动态逐次逼近控制逻辑,降低了模数转换器的功耗和面积。流片测试结果表明,在1.8V电源电压,50MS/s采样速率下,信噪失真比(SFDR)和功耗分别为56.04dB和5mV。

A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS

A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC. The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy. The SAR-based and "half-gain" MDAC reduce the power consumption and core area. The dynamic comparator and SAR control logic are applied to reduce power consumption. Implemented in 180 nm CMOS, the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.