Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation |
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Authors: | Yu-Sheng Lin Chia-Hong Lin Kuo J.B. Ke-Wei Su |
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Affiliation: | Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan; |
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Abstract: | This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step C/sub S(D)G//C/sub GS/ versus V/sub G/ curve could be identified for the device with the 1.5-nm HfO/sub 2/ gate dielectric due to the vertical and fringing displacement effects. |
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