面向高带宽I/O的片上网络优化

在高性能处理器中,I/O带宽需求不断增加,一方面高速接口的通道数目不断增加,另一方面接口传输速率也在逐渐提升.高性能处理器的片上网络必须能够匹配各种高速I/O的带宽需求,且必须保证DM A请求能够正确完成.然而各种高速接口协议与片上网络协议在通信机制上存在较大的差别,可能导致死锁等现象的产生.首先对匹配高性能I/O的片...

Network-on-Chip optimization for high bandwidth I/O in processors

In high-performance processors, the demand of I/O bandwidth is increasing. On the one hand, more and more lanes of high-speed interface are used, and on the other hand the transmission rate of interface is also raised gradually. The Network-on-Chip (NoC) of high-performance processors must be able to match the bandwidth requirements of various high-speed I/O interface, and must ensure that direct memory access (DMA) requests can be completed correctly. However, there are great differences in communication mechanism between various high-speed interface protocols and interconnection network protocols, which may lead to deadlock and other problems. This paper first analyzes NoC and high performance I/O, and proposes a method of designing high bandwidth I/O interface and a solution of resolving deadlock. NoC with deadlock resolution technique makes the I/O system more robust, and various limitations of NoC design can be reduced. Finally, based on a server processor, the proposed optimization method was implemented and evaluated. For 16-lane PCIe Gen4 interface, the read and write bandwidths reach up to 30GB/s respectively. In some special scenarios, deadlock is produced due to special transaction sequences, and the NoC can automatically detect the deadlock and release the deadlock.