HEVC中率失真优化算法的动态可重构实现

基于视频阵列处理器高效视频编码HEVC实现中,HEVC灵活的编码块增加了率失真优化算法硬件实现的难度,难以实现阵列规模和不同块的灵活切换.针对这一问题,提出一种动态可重构的率失真优化实现方法.基于上下文切换的动态重构机制,完成不同规模、不同块大小算法之间的灵活切换,并以率失真优化算法作为帧内模式选择的判别依据,实现帧内...

Dynamic reconfigurable implementation of rate distortion optimization algorithm in HEVC

In the implementation based on video array processor, the flexible coding blocks of High Efficiency Video Coding (HEVC) increase the difficulty of hardware implementation of the rate-distortion optimization algorithm, and it is difficult to realize the array size and flexible switching of different blocks. Aiming at this problem, a dynamic reconfigurable implementation method of rate- distortion optimization is proposed. The dynamicreconfiguration mechanism based on context switching completes the flexible switching among algorithms of different sizes and different block sizes, and uses the rate-distortion optimization algorithm as the basis of discriminating the intra-mode selection to realize the intra-prediction mode reconfiguration. Experimental results show that, compared with the rate- distortion optimization algorithm implemented by dedicated hardware, when the algorithm is flexibly switched, the hardware area is reduced by 8.2%, and the number of clock cycles of algorithm execution is reduced by 165%.