基于FPGA的卷积神经网络加速器动态余数处理映射模型

将卷积计算转化为矩阵乘法是FPGA上一种高效实现,而现有的转化方法无法根据卷积参数的不同动态调整,限制了卷积计算的并行度.提出一种新的动态余数处理映射模型.该映射模型包含有3个子模型:特征值映射模型,权值映射模型,和输出映射模型.特征值映射模型将特征值转化为特征值矩阵,权值映射模型将权值转化为权值矩阵,特征值矩阵和权值矩阵通过乘累加计算阵列得到卷积计算结果,由输出映射模型将卷积计算结果存储到内存中.在卷积计算过程中,卷积的输出通道数通常不是乘累加计算阵列行数的整数倍,3个子映射模型会根据产生的余数动态调整映射方法,提高乘累加计算阵列的利用率.通过实验表明,采用动态余数处理映射模型能够将余数并行度的倍数至多提高到卷积核大小,使整个加速器达到了更高的实际吞吐量和能量效率.

A dynamic remainder processing mapping model for convolutional neural network accelerator on FPGA

Mapping convolutions to matrix multiplications is an efficient implementation on FPGA. However, the existing conversion methods cannot be dynamically adjusted according to different convolution parameters, which limits the parallelism of convolution calculation. This paper proposes a novel dynamic residue processing mapping model. The mapping model contains three sub-models: feature mapping model, weight mapping model, and output mapping model. The feature mapping model converts features into a feature matrix, and the weight mapping model converts weights into a weight matrix. The feature matrix and the weight matrix obtain convolution calculation results by multiply-and- accumulate array, and the convolution calculation results are stored in the memory by the output mapping model. In the process of convolution calculation, the number of output channels of the convolution is usually not an integer multiple of the number of rows of the multiply-and-accumulate array. The three sub-mapping models will dynamically adjust the mapping method according to the remaining number to increase the utilization of the multiply-accumulated array. Experiments show that using the dynamic remainder processing mapping model can increase the multiple of parallelism up to the size of the convolution kernel and achieve higher actual throughput and energy efficiency.