| 基于FPGA的H.264解码IP核中CAVLC熵解码模块的设计 |
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| 引用本文： | 杨炎思,王霞.基于FPGA的H.264解码IP核中CAVLC熵解码模块的设计[J].中国有线电视,2021(1). |
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| 作者姓名： | 杨炎思 王霞 |
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| 作者单位： | 江西广播电视台 |
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| 摘 要： | 提出了一种基于FPGA的H.264视频解码的IP核设计方案,对以NIOS Ⅱ软件处理器为内核的SOPC系统进行了优化,对CAVLC熵解码进行了优化。CAVLC熵解码模块硬件加速的方法,与无硬件加速的NIOS Ⅱ软件解码方法相比,缩短了解码耗时,使基于FPGA的H.264视频实时解码和播放成为可能。
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| 关 键 词： | H.264 NIOSⅡ SOPC IP core CAVLC |
Design of CAVLC Entropy Decoding Module in H.264 Video Decoding IP Core Based on FPGA |
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| YANG Yansi,WANG Xia.Design of CAVLC Entropy Decoding Module in H.264 Video Decoding IP Core Based on FPGA[J].China Cable Television,2021(1). |
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| Authors: | YANG Yansi WANG Xia |
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| Affiliation: | (Jiangxi Radio and TV Station,Nanchang 330029,China) |
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| Abstract: | This paper presents a design of IP core used in H.264 video decoding based on FPGA, which optimizes the SOPC system with NIOS Ⅱ software processor being the kernel. This design contributes to the optimization of the CAVLC entropy decoding module. The methodology of hardware acceleration to CAVLC entropy decoding module, which compared to the decoding method exerted by NIOS Ⅱ software without the assistance of hardware acceleration, shrinks the span of time consumed. The methodology make it possible to realize the real-time H.264 video decoding and playing based on FPGA. |
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| Keywords: | H 264 NIOSⅡ SOPC IP core CAVLC |
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