A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro |
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| Authors: | Takeda K. Aimoto Y. Nakamura N. Toyoshima H. Iwasaki T. Noda K. Matsui K. Itoh S. Masuoka S. Horiuchi T. Nakagawa A. Shimogawa K. Takahashi H. |
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| Affiliation: | Dept. of Syst. Devices & Fundamental Res., NEC Corp., Kanagawa; |
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| Abstract: | We have used a 5-metal 0.18-μm CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-μm gate length |
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