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用于多通道数据传输的SDRAM控制器设计与实现
引用本文:王鹏,郭琪,徐东明.用于多通道数据传输的SDRAM控制器设计与实现[J].中国集成电路,2009,18(1):49-53.
作者姓名:王鹏  郭琪  徐东明
作者单位:西安邮电学院,电子与信息工程系,陕西,西安,710061
摘    要:介绍了SDRAM的结构和控制时序特点。阐明了SDRAM控制器在多通道数据传输中的电路对齐应用,并针对传输过程中各通道产生的数据延时提出了一种可行性的解决方案。最后根据SDRAM的基本控制命令,结合实际系统需要以及多通路数据采集中的FPGA和SDRAM接口设计要求,设计完成了一款高速、灵活的SDRAM控制器,并且为了便于后期调试,加入了SDRAM自检模式。仿真顺利通过并在硬件上调试成功。

关 键 词:SDRAM  VerilogHDL  自检测  通道添加  延时调整

SDRAM Controler Design in the Muti-channel Data Transmission
WANG Peng,GUO Qi,XU Dong-ming.SDRAM Controler Design in the Muti-channel Data Transmission[J].China Integrated Circuit,2009,18(1):49-53.
Authors:WANG Peng  GUO Qi  XU Dong-ming
Affiliation:(Department of Electronic and Information Engineering ,Xi'an institute of post and telecommunication, Xi'an 710061,China)
Abstract:The structure and control timing characteristics are introduced in this paper. It described the key technology of SDRAM controller in the multi-channel data transmission and a feasibility resolution based on the differential delay of the data in multi-channel. This article complete a high-speed,flexible SDRAM controller,which is based on the basic control command and principles of adding channels in the multi-channel data transmission,according to the actual requirement of the system and data collection in FPGA and SDRAM interface design. SDRAM self-diagnostic mode is added which is convenient for the FPGA test. The simulation results are provided to verify analytical results.
Keywords:SDRAM  Veri1ogHDL
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