A nonvolatile analog neural memory using floating-gate MOS transistors |
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Authors: | Han Yang Bing J Sheu Ji-Chien Lee |
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Affiliation: | (1) Department of Electrical Engineering, National Center for Integrated Photonic Technology, University of Southern California, 90089-0271 Los Angeles, CA |
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Abstract: | Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 m×73 m in a 2- m CMOS process and can retain charge accuracy for over 25 years.This research was partially supported by DARPA under Contracts MDA972-90-C-0037 and MDA972-88-C-0048 and by TRW, Inc. |
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