| STG-BASED VERIFICATION AND TEST GENERATION |
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| 引用本文： | He Xinhua Gong Yunzhan(Armoured Force Engineering Institute,Beijing 100072)Wei Daozheng (CAD Lab,Institute of Computing Technology Academia Sinica,Beijing 100080). STG-BASED VERIFICATION AND TEST GENERATION[J]. 电子科学学刊(英文版), 1996, 13(1): 68-73. DOI: 10.1007/BF02684717 |
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| 作者姓名： | He Xinhua Gong Yunzhan(Armoured Force Engineering Institute Beijing 100072)Wei Daozheng (CAD Lab Institute of Computing Technology Academia Sinica Beijing 100080) |
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| 作者单位： | He Xinhua Gong Yunzhan(Armoured Force Engineering Institute，Beijing 100072)Wei Daozheng (CAD Lab，Institute of Computing Technology Academia Sinica，Beijing 100080) |
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| 基金项目： | Supported by the National Natural science Foundation of China(No.69576038) |
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| 摘 要： | This paper presents the techniques of verification and Test Generation(TG) for sequential machines (Finite State Machines, FSMs) based on state traversing of State Transition Graph(STG). The problems of traversing, redundancy and transition fault model are identified. In order to achieve high fault coverage collapsing testing is proposed. Further, the heuristic knowledge for speeding up verification and TG are described.
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STG-based verification and test generation |
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| He Xinhua,Gong Yunzhan,Wei Daozheng. STG-based verification and test generation[J]. Journal of Electronics, 1996, 13(1): 68-73. DOI: 10.1007/BF02684717 |
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| Authors: | He Xinhua Gong Yunzhan Wei Daozheng |
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| Affiliation: | (1) Armoured Force Engineering Institute, 100072 Beijing;(2) CAD Lab, Institute of Computing Technology Academia Sinica, 100080 Beijing |
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| Abstract: | This paper presents the techniques of verification and Test Generation(TG) for sequential machines (Finite State Machines, FSMs) based on state traversing of State Transition Graph(STG). The problems of traversing, redundancy and transition fault model are identified. In order to achieve high fault coverage collapsing testing is proposed. Further, the heuristic knowledge for speeding up verification and TG are described. |
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| Keywords: | Verification Test generation Traversing State transition graph |
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